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general description the MAX7314 i 2 c-compatible serial interfaced periph- eral provides microprocessors with 16 i/o ports plus one output-only port and one input-only port. each i/o port can be individually configured as either an open-drain current-sinking output rated at 50ma and 5.5v, or a logic input with transition detection. the output-only port can be assigned as an interrupt output for transition detec- tion. the outputs are capable of driving leds, or provid- ing logic outputs with external resistive pullup up to 5.5v. eight-bit pwm current control is built in for all 17 output ports. a 4-bit global control applies to all led outputs and provides coarse adjustment of current from fully off to fully on with 14 intensity steps in between. each out- put has an individual 4-bit control, which further divides the globally set current into 16 more steps. alternatively, the current control can be configured as a single 8-bit control that sets all outputs at once. each output has independent blink timing with two blink phases. all leds can be individually set to be on or off during either blink phase, or to ignore the blink control. the blink period is controlled by a clock input (up to 1khz) on blink or by a register. the blink input can also be used as a logic control to turn the leds on and off, or as a general-purpose input. the MAX7314 supports hot insertion. all port pins, the int output, sda, scl, rst , blink, and the slave address input ado remain high impedance in power- down (v+ = 0v) with up to 6v asserted upon them. the MAX7314 is controlled through a 2-wire serial inter- face, and uses four-level logic to allow four i 2 c addresses from only one select pin. applications lcd backlights led status indication relay drivers keypad backlights rgb led drivers system i/o ports features ? 400kbps, 2-wire serial interface, 5.5v tolerant ? 2v to 3.6v operation ? overall 8-bit pwm led intensity control global 16-step intensity control individual 16-step intensity controls ? 2-phase led blinking ? 50ma maximum port output current ? supports hot insertion ? outputs are 5.5v-rated open drain ? inputs are overvoltage protected to 5.5v ? transition detection with interrupt output ? 1.2? (typ), 3.6? (max) operating current ? small 4mm x 4mm, thin qfn package ? -40? to +125? temperature range MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ________________________________________________________________ maxim integrated products 1 MAX7314 p8 p10 p0 p1 p2 p3 p4 p5 p6 p7 v+ 3.3v c sda sda ad0 3.3v 5v p11 p12 p13 p14 p15 scl scl blink i/o rst i/o p9 output output gnd 5v input 1 input 2 input 3 input 4 input 5 0.047 f int int/o16 typical application circuit 19-3170; rev 4; 4/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package pkg code MAX7314atg -40 c to +125 c 24 thin qfn 4mm x 4mm x 0.8mm t2444-4 MAX7314aeg -40 c to +125 c 24 qsop pin configurations continued at end of data sheet. i 2 c is a trademark of philips corp. purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these compo- nents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +4v scl, sda, ad0, blink, rst , p0?15 .....................-0.3v to +6v int /o16 ...................................................................-0.3v to +8v dc current on p0?15, int /o16 ........................................55ma dc current on sda.............................................................10ma maximum gnd current ....................................................350ma continuous power dissipation (t a = +70?) 24-pin qsop (derate 9.5mw/? over +70?)..............761mw 24-pin qfn (derate 20.8mw/? over +70?) ............1666mw operating temperature range (t min to t max ) .............................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ 2 3.6 v output load external supply voltage v ext 0 5.5 v t a = +25? 1.2 2.3 t a = -40? to +85? 2.8 standby current (interface idle, pwm disabled) i + s c l and s d a at v + ; other d i g i tal i np uts at v + or gn d ; p wm i ntensi ty contr ol d i sab l ed t a = t min to t max 3.6 ? t a = +25? 8.5 15.1 t a = -40? to +85? 16.5 supply current (interface idle, pwm enabled) i + s c l and s d a at v + ; other d i g i tal i np uts at v + or gn d ; p wm i ntensi ty contr ol d i sab l ed t a = t min to t max 17.2 ? t a = +25? 50 95.3 t a = -40? to +85? 99.2 supply current (interface running, pwm disabled) i + f scl = 400khz; other digital inputs at v+ or gnd; pwm intensity control enabled t a = t min to t max 102.4 ? t a = +25? 57 110.2 t a = -40? to +85? 117.4 supply current (interface running, pwm enabled) i + f scl = 400khz; other digital inputs at v+ or gnd; pwm intensity control enabled t a = t min to t max 122.1 ? input high voltage sda, scl, ad0, blink, p0?15 v ih 0.7 x v+ v input low voltage sda, scl, ad0, blink, p0?15 v il 0.3 x v+ v input leakage current sda, scl, ad0, blink, p0?15 i ih , i il 0 input voltage 5.5v -0.2 +0.2 ? input capacitance sda, scl, ad0, blink, p0?15 8pf
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 3 electrical characteristics (continued) (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = + 25?.) (note 1) parameter symbol conditions min typ max units t a = +25? 0.15 0.26 t a = -40? to +85? 0.3 v+ = 2v, i sink = 20ma t a = t min to t max 0.32 v t a = +25? 0.13 0.23 t a = -40? to +85? 0.26 v+ = 2.5v, i sink = 20ma t a = t min to t max 0.28 v t a = +25? 0.12 0.23 t a = -40? to +85? 0.24 output low voltage p0?15, int /o16 v ol v+ = 3.3v, i sink = 20ma t a = t min to t max 0.26 v output low-voltage sda v olsda i sink = 6ma 0.4 v pwm clock frequency f pwm 32 khz timing characteristics (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time, repeated start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 2) 0.9 ? data setup time t su , dat 180 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and scl signals, receiving t r (notes 3, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 3, 4) 20 + 0.1c b 300 ns fall time of sda transmitting t f.tx (notes 3, 5) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 6) 50 ns capacitive load for each bus line c b (note 3) 400 pf rst pulse width t w 1s
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection 4 _______________________________________________________________________________________ timing characteristics (continued) (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units interrupt valid t iv figure 10 6.5 ? interrupt reset t ir figure 10 1 s output data valid t dv figure 10 5 s input data set-up time t ds figure 10 100 ns input data hold time t dh figure 10 1 s note 1: all parameters tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 3: guaranteed by design. note 4: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 x v dd and 0.7 x v dd . note 5: i sink 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 x v dd and 0.7 x v dd . note 6: input filters on the sda and scl inputs suppress noise spikes less than 50ns. standby current vs. temperature MAX7314 toc01 temperature ( c) standby current ( a) 110 95 65 80 -10 5 20 35 50 -25 1 2 3 4 5 6 7 8 9 10 0 -40 125 v+ = 3.6v pwm enabled v+ = 2.7v pwm enabled v+ = 2v pwm disabled v+ = 2.7v pwm disabled v+ = 3.6v pwm disabled v+ = 2v pwm enabled supply current vs. temperature (pwm disabled; f scl = 400khz) MAX7314 toc02 temperature ( c) supply current ( a) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 70 0 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0 supply current vs. temperature (pwm enabled; f scl = 400khz) MAX7314 toc03 temperature ( c) supply current ( a) 110 95 65 80 -10 5 20 35 50 -25 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.)
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 5 port output low voltage with 50ma load current vs. temperature port output low voltage v ol (v) 0.1 0.2 0.3 0.4 0.5 0.6 0 MAX7314 toc04 temperature ( c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v port output low voltage with 20ma load current vs. temperature MAX7314 toc05 temperature ( c) port output low voltage v ol (v) 110 95 80 65 50 35 20 5 -10 -25 0.1 0.2 0.3 0.4 0.5 0.6 0 -40 125 all outputs loaded v+ = 3.6v v+ = 2.7v v+ = 2v pwm clock frequency vs. temperature MAX7314 toc06 temperature ( c) pwm clock frequency (khz) 110 95 80 65 50 35 20 5 -10 -25 0.950 1.000 1.050 0.900 0.925 0.975 1.025 -40 125 v+ = 3.6v v+ = 2v v+ = 2.7v normalized to v+ = 3.3v, t a = +25 c scope shot of 2 output ports MAX7314 toc07 2ms/div output 1, 2v/div output 2, 2v/div master intensity set to 1/15 output 1 individual intensity set to 1/16 output 2 individual intensity set to 15/16 scope shot of 2 output ports MAX7314 toc08 2ms/div output 1 2v/div output 2 2v/div output 1 individual intensity set to 1/16 master intensity set to 14/15 output 2 individual intensity set to 14/15 MAX7314 toc09 sink current vs. v ol sink current (ma) v ol (v) 50 40 30 20 10 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 045 35 25 15 5 v+ = 2v v+ = 2.7v only one output loaded v+ = 3.3v v+ = 3.6v typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
MAX7314 functional overview the MAX7314 is a general-purpose input/output (gpio) peripheral that provides 16 i/o ports, p0?15, con- trolled through an i 2 c-compatible serial interface. a 17th output-only port, int /o16, can be configured as an interrupt output or as a general-purpose output port. all output ports sink loads up to 50ma connected to external supplies up to 5.5v, independent of the MAX7314? supply voltage. the MAX7314 is rated for a ground current of 350ma, allowing all 17 outputs to sink 20ma at the same time. figure 1 shows the output structure of the MAX7314. the ports default to inputs on power-up. 18-port gpio with led intensity control, interrupt, and hot-insertion protection 6 _______________________________________________________________________________________ pin description figure 1. simplified schematic of i/o ports d c k q q ff data from shift register data from shift register write configuration pulse write pulse read pulse configuration register d c k q q ff input port register d c k q q ff output port register output port register data i/o pin q2 gnd input port register data to int pin qsop qfn name function 122 int /o16 output port. open-drain output rated at 7v, 50ma. configurable as interrupt output or general-purpose output. 223 rst reset input. active low clears the 2-wire interface and puts the device in the same condition as power-up reset. 3 24 ad0 address input. sets device slave address. connect to either gnd, v+, scl, or sda to give four logic combinations. see table 1. 4?1, 13?0 1?, 10?7 p0?15 input/output ports. p0?15 are open-drain i/os rated at 5.5v, 50ma. 12 9 gnd ground. do not sink more than 350ma into the gnd pin. 21 18 blink input port configurable as blink control or general-purpose input 22 19 scl i 2 c-compatible serial clock input 23 20 sda i 2 c-compatible serial data i/o 24 21 v+ positive supply voltage. bypass v+ to gnd with a 0.047? ceramic capacitor. pad exposed pad exposed pad on package underside. connect to gnd.
port inputs and transition detection input ports registers reflect the incoming logic levels of the port pins, regardless of whether the pin is defined as an input or an output. reading an input ports regis- ter latches the current-input logic level of the affected eight ports. transition detection allows all ports config- ured as inputs to be monitored for changes in their logic status. the action of reading an input ports regis- ter samples the corresponding 8 port bits?input condi- tion. this sample is continuously compared with the actual input conditions. a detected change in input condition causes the int /o16 interrupt output to go low, if configured as an interrupt output. the interrupt is cleared either automatically if the changed input returns to its original state, or when the appropriate input ports register is read. the int /o16 pin can be configured as either an inter- rupt output or as a 17th output port with the same static or blink controls as the other 16 ports (table 4). port output control and led blinking the two blink phase 0 registers set the output logic lev- els of the 16 ports p0?15 (table 8). these registers control the port outputs if the blink function is disabled. a duplicate pair of registers, the blink phase 1 registers, are also used if the blink function is enabled (table 9). in blink mode, the port outputs can be flipped between using the blink phase 0 registers and the blink phase 1 registers using hardware control (the blink input) and/or software control (the blink flip flag in the configu- ration register) (table 4). the logic level of the blink input can be read back through the blink status bit in the configuration register (table 4). the blink input, therefore, can be used as a general-purpose logic input (gpi port) if the blink function is not required. pwm intensity control the MAX7314 includes an internal oscillator, nominally 32khz, to generate pwm timing for led intensity control. pwm intensity control can be enabled on an output-by- output basis, allowing the MAX7314 to provide any mix of pwm led drives and glitch-free logic outputs (table 10). pwm can be disabled entirely, in which case all out- put ports are static and the MAX7314 operating current is lowest because the internal oscillator is turned off. pwm intensity control uses a 4-bit master control and 4 bits of individual control per output (tables 13, 14). the 4-bit master control provides 16 levels of overall intensi- ty control, which applies to all pwm-enabled output ports. the master control sets the maximum pulse width from 1/15 to 15/15 of the pwm time period. the individual settings comprise a 4-bit number, further reducing the duty cycle to be from 1/16 to 15/16 of the time window set by the master control. for applications requiring the same pwm setting for all output ports, a single global pwm control can be used instead of all the individual controls to simplify the con- trol software and provide 240 steps of intensity control (tables 10 and 13). standby mode when the serial interface is idle and the pwm intensity control is unused, the MAX7314 automatically enters standby mode. if the pwm intensity control is used, the operating current is slightly higher because the internal pwm oscillator is running. when the serial interface is active, the operating current also increases because the MAX7314, like all i 2 c slaves, has to monitor every transmission. MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 7 figure 2. 2-wire serial interface timing details scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta
MAX7314 serial interface serial addressing the MAX7314 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the MAX7314 and generates the scl clock that synchronizes the data transfer (figure 2). the MAX7314 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on the sda. the MAX7314 scl line oper- ates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master sys- tem has an open-drain scl output. each transmission consists of a start condition (figure 3) sent by a master, followed by the MAX7314 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally a stop condi- tion (figure 3). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 4). acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data (figure 5). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse so the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the MAX7314, the device gen- erates the acknowledge bit because the MAX7314 is the recipient. when the MAX7314 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave address the MAX7314 has a 7-bit long slave address (figure 6). the eighth bit following the 7-bit slave address is the r/ w bit. the r/ w bit is low for a write command, high for a read command. 18-port gpio with led intensity control, interrupt, and hot-insertion protection 8 _______________________________________________________________________________________ figure 3. start and stop conditions sda scl start condition stop condition sp figure 4. bit transfer sda scl data line stable; data valid change of data allowed figure 5. acknowledge scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 12 89 s figure 6. slave address sda scl 1 msb lsb ack 00 a6 0 0 a2 r/w
the second (a5), third (a4), fourth (a3), sixth (a1), and last (a0) bits of the MAX7314 slave address are always 1, 0, 0, 0, and 0. slave address bits a6 and a2 are selected by the address input ad0. ad0 can be con- nected to gnd, v+, sda, or scl. the MAX7314 has four possible slave addresses (table 1), and therefore a maximum of four MAX7314 devices can be controlled independently from the same interface. message format for writing the MAX7314 a write to the MAX7314 comprises the transmission of the MAX7314? slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte. the com- mand byte determines which register of the MAX7314 is to be written to by the next byte, if received (table 2). if a stop condition is detected after the command byte is received, then the MAX7314 takes no further action beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the MAX7314 selected by the command byte (figure 8). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent MAX7314 internal registers because the command byte address autoincrements (table 2). a diagram of a write to the output ports registers (blink phase 0 registers or blink phase 1 registers) is given in figure 10. MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 9 table 1. MAX7314 address map device address pin ad0 a6 a5 a4 a3 a2 a1 a0 scl 1100000 sda1100100 gnd0100000 v+ 0100100 figure 8. command and single data byte received saaap 0 slave address command byte data byte 1 byte autoincrement memory address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from MAX7314 acknowledge from MAX7314 acknowledge from MAX7314 how command byte and data byte map into MAX7314's registers r/w figure 9. n data bytes received saaap 0 slave address command byte data byte n bytes autoincrement memory address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from MAX7314 acknowledge from MAX7314 acknowledge from MAX7314 how command byte and data byte map into MAX7314's registers r/w figure 7. command byte received saap 0 slave address command byte acknowledge from MAX7314 d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition acknowledge from MAX7314 r/w
MAX7314 message format for reading the MAX7314 is read using the MAX7314? internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write (table 2). thus, a read is initiated by first configur- ing the MAX7314? command byte by performing a write (figure 7). the master can now read n consecu- tive bytes from the MAX7314 with the first data byte being read from the register addressed by the initial- ized command byte. when performing read-after-write verification, remember to reset the command byte? address because the stored command byte address has been autoincremented after the write (table 2). a diagram of a read from the input ports registers is shown in figure 10 reflecting the states of the ports. operation with multiple masters if the MAX7314 is operated on a 2-wire interface with multiple masters, a master reading the MAX7314 should use a repeated start between the write, which sets the MAX7314? address pointer, and the read(s) that takes the data from the location(s) (table 2). this is because it is possible for master 2 to take over the bus after master 1 has set up the MAX7314? address pointer but before master 1 has read the data. if master 2 subsequently changes the MAX7314? address pointer, then master 1? delayed read can be from an unexpect ed location. command address autoincrementing the command address stored in the MAX7314 circu- lates around grouped register functions after each data byte is written or read (table 2). 18-port gpio with led intensity control, interrupt, and hot-insertion protection 10 ______________________________________________________________________________________ figure 10. read, write, and interrupt timing diagrams slave address 123456789 sa6a5a4a3a2a1a00a0 000000 command byte 1a a ap start condition acknowledge from slave acknowledge from slave acknowledge from slave stop condition p7?0 p15?p8 data1 valid data2 valid slave address 123456789 s a6a5a4a3a2a1a0 1 a command byte ana start condition acknowledge from slave acknowledge from master p7?0 p15?8 stop condition p no acknowledge from master data2 data4 data3 t dv t dv slave address 123456789 sa6a5a4a3a2a1a0 1 a command byte ana start condition acknowledge from slave acknowledge from master p7?0 p15?8 stop condition p no acknowledge from master data1 data2 data3 data4 data6 data5 t dh t ds data1 t iv t ir t ir t iv scl sda scl sda scl sda write to output ports registers (blink phase 0 registers/blink phase 1 registers) read from input ports registers interrupt valid/reset r/w msb lsb data1 msb lsb data1 msb lsb data2 msb lsb data4 msb lsb data6 msb lsb data2 r/w r/w int
device reset the reset input rst is an active-low input. when taken low, rst clears any transaction to or from the MAX7314 on the serial interface and configures the internal regis- ters to the same state as a power-up reset (table 3), which resets all ports as inputs. the MAX7314 then waits for a start condition on the serial interface. detailed description initial power-up on power-up, and whenever the rst input is pulled low, all control registers are reset and the MAX7314 enters standby mode (table 3). power-up status makes all ports into inputs and disables both the pwm oscilla- tor and blink functionality. rst can be used as a hard- ware shutdown input, which effectively turns off any led (or other) loads and puts the device into its lowest power condition. configuration register the configuration register is used to configure the pwm intensity mode, interrupt, and blink behavior, operate the int /o16 output, and read back the interrupt status (table 4). ports configuration the 16 i/o ports p0 through p15 can be configured to any combination of inputs and outputs using the ports configuration registers (table 5). the int /o16 output can also be configured as an extra general-purpose output, and the blink input can be configured as an extra general-purpose input using the configuration register (table 4). input ports the input ports registers are read only (table 6). they reflect the incoming logic levels of the ports, regardless of whether the port is defined as an input or an output by the ports configuration registers. reading an input ports reg- ister latches the current-input logic level of the affected eight ports. a write to an input ports register is ignored. MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 11 table 2. register address map register address code (hex) autoincrement address read input ports p7?0 0x00 0x01 read input ports p15?8 0x01 0x00 blink phase 0 outputs p7?0 0x02 0x03 blink phase 0 outputs p15?8 0x03 0x02 ports configuration p7?0 0x06 0x07 ports configuration p15?8 0x07 0x06 blink phase 1 outputs p7?0 0x0a 0x0b blink phase 1 outputs p15?8 0x0b 0x0a master, o16 intensity 0x0e 0x0e (no change) configuration 0x0f 0x0f (no change) outputs intensity p1, p0 0x10 0x11 outputs intensity p3, p2 0x11 0x12 outputs intensity p5, p4 0x12 0x13 outputs intensity p7, p6 0x13 0x14 outputs intensity p9, p8 0x14 0x15 outputs intensity p11, p10 0x15 0x16 outputs intensity p13, p12 0x16 0x17 outputs intensity p15, p14 0x17 0x10
MAX7314 transition detection all ports configured as inputs are always monitored for changes in their logic status. the action of reading an input ports register or writing to the configuration regis- ter samples the corresponding 8 port bits?input condi- tion (tables 4, 6). this sample is continuously compared with the actual input conditions. a detected change in input condition causes an interrupt condition. the interrupt is cleared either automatically if the changed input returns to its original state, or when the appropriate input ports register is read, updating the compared data (figure 10). randomly changing a port from an output to an input may cause a false interrupt to occur if the state of the input does not match the content of the appropriate input ports register. the interrupt status is available as the interrupt flag int in the configuration register (table 4). the input status of all ports is sampled immediately after power-up as part of the MAX7314? internal initial- ization, so if all the ports are pulled to valid logic levels at that time, an interrupt does not occur at power-up. int /o16 output the int /o16 output pin can be configured as either the int output that reflects the interrupt flag logic state or as a general-purpose output o16. when used as a general- purpose output, the int /o16 pin has the same blink and pwm intensity control capabilities as the other ports. set the interrupt enable i bit in the configuration register to configure int /o16 as the int output (table 4). clear interrupt enable to configure int /o16 as the o16. the o16 logic state is set by the 2 bits o1 and o0 in the configuration register. o16 follows the rules for blinking selected by the blink enable flag e in the configuration register. if blinking is disabled, then interrupt output control o0 alone sets the logic state of the int /o16 pin. if blinking is enabled, then both interrupt output con- trols o0 and o1 set the logic state of the int /o16 pin according to the blink phase. pwm intensity control for o16 is set by the 4 global intensity bits in the master and o16 intensity register (table 13). 18-port gpio with led intensity control, interrupt, and hot-insertion protection 12 ______________________________________________________________________________________ table 3. power-up configuration register data register function power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 blink phase 0 outputs p7?0 high-impedance outputs 0x02 1 1 1 1 1 1 1 1 blink phase 0 outputs p15?8 high-impedance outputs 0x03 1 1 1 1 1 1 1 1 ports configuration p7?0 ports p7?0 are inputs 0x06 1 1 1 1 1 1 1 1 ports configuration p15?8 ports p15?8 are inputs 0x07 1 1 1 1 1 1 1 1 blink phase 1 outputs p7?0 high-impedance outputs 0x0a 1 1 1 1 1 1 1 1 blink phase 1 outputs p15?8 high-impedance outputs 0x0b 1 1 1 1 1 1 1 1 master, o16 intensity pwm oscillator is disabled; o16 is static logic output 0x0e 0 0 0 0 1 1 1 1 configuration int /o16 is interrupt output; blink is disabled; global intensity is enabled 0x0f 0 0 0 0 1 1 0 0 outputs intensity p1, p0 p1, p0 are static logic outputs 0x10 1 1 1 1 1 1 1 1 outputs intensity p3, p2 p3, p2 are static logic outputs 0x11 1 1 1 1 1 1 1 1 outputs intensity p5, p4 p5, p4 are static logic outputs 0x12 1 1 1 1 1 1 1 1 outputs intensity p7, p6 p7, p6 are static logic outputs 0x13 1 1 1 1 1 1 1 1 outputs intensity p9, p8 p9, p8 are static logic outputs 0x14 1 1 1 1 1 1 1 1 outputs intensity p11, p10 p11, p10 are static logic outputs 0x15 1 1 1 1 1 1 1 1 outputs intensity p13, p12 p13, p12 are static logic outputs 0x16 1 1 1 1 1 1 1 1 outputs intensity p15, p14 p15, p14 are static logic outputs 0x17 1 1 1 1 1 1 1 1
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 13 table 4. configuration register register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 configuration r/ w 0x0f interrupt status blink status interrupt output control as gpo interrupt enable global intensity blink flip blink enable write device configuration 0 read back device configuration 1 int blink o1 o0 i g b e disable blink xxxxxxx 0 enable blink xxxxxxx 1 xxxxxx 01 flip blink register (see text) xxxxxx 11 disable global intensity control?ntensity is set by registers 0x10?x17 for ports p0 through p15 when configured as outputs, and by d3?0 of register 0x0e for int /o16 when int /o16 pin is configured as an output port xxxxx 0 xx enable global intensity control?ntensity for all ports configured as outputs is set by d3?0 of register 0x0e xxxxx 1 xx disable data change interrupt int /o16 output is controlled by the o0 and o1 bits xxxx 0 xxx enable data change interrupt int /o16 output is controlled by port input data change xxxx 1 xxx int /o16 output is low (blink is disabled) xxx 00 xx 0 int /o16 output is high impedance (blink is disabled) xxx 10 xx 0 int /o16 outp ut i s l ow d ur i ng b l i nk p hase 0 xxx 00 xx 1 int /o16 output is high impedance during blink phase 0 xxx 10 xx 1 int /o16 outp ut i s l ow d ur i ng b l i nk p hase 1 xx 0 x 0 xx 1 int /o16 output is high impedance during blink phase 1 xx 1 x 0 xx 1 x = don? care.
MAX7314 blink mode in blink mode, the output ports can be flipped between using either the blink phase 0 registers or the blink phase 1 registers. flip control is both hardware (the blink input) and software control (the blink flip flag b in the configuration register) (table 4). the blink function can be used for led effects by pro- gramming different display patterns in the two sets of output port registers, and using the software or hard- ware controls to flip between the patterns. if the blink phase 1 registers are written with 0xff, then the blink input can be used as a hardware disable to, for example, instantly turn off an led pattern pro- grammed into the blink phase 0 registers. this tech- nique can be further extended by driving the blink input with a pwm signal to modulate the led current to provide fading effects. the blink mode is enabled by setting the blink enable flag e in the configuration register (table 4). when blink mode is enabled, the states of the blink flip flag and the blink input are exor?d to set the phase, and the output ports are set by either the blink phase 0 registers or the blink phase 1 registers (figure 11) (table 7). the blink mode is disabled by clearing the blink enable flag e in the configuration register (table 4). when blink mode is disabled, the state of the blink flip flag is ignored, and the blink phase 0 registers alone control the output ports. blink phase registers when the blink function is disabled, the two blink phase 0 registers set the logic levels of the 16 ports (p0 through p15) when configured as outputs (table 8). a duplicate pair of registers called the blink phase 1 reg- isters are also used if the blink function is enabled (table 9). a logic high sets the appropriate output port high impedance, while a logic low makes the port go low. 18-port gpio with led intensity control, interrupt, and hot-insertion protection 14 ______________________________________________________________________________________ table 4. configuration register (continued) register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 configuration r/ w interrupt status blink status interrupt output control as gpo interrupt enable global intensity blink flip blink enable write device configuration 0 read back device configuration 1 int blink o1 o0 igbe read back blink input pin status input is low 1 x 0 xxxxxx read back blink input pin status input is high 1 x 1 xxxxxx read b ack d ata chang e i nter r up t status ? d ata chang e i s not d etected , and int /o16 outp ut i s hi g h w hen i nter r up t enab l e ( i b i t) i s set 1 0 xxxxxxx read b ack d ata chang e i nter r up t status ? ata chang e i s d etected , and int /o16 outp ut i s l ow w hen i nter r up t enab l e ( i b i t) i s set 1 0x0f 1 xxxxxxx x = don? care. blink phase registers blink input blink flip flag b blink enable flag e figure 11. blink logic
reading a blink phase register reads the value stored in the register, not the actual port condition. the port output itself may or may not be at a valid logic level, depending on the external load connected. the 17th output, o16, is controlled through 2 bits in the configuration register, which provide the same static or blink control as the other 16 output ports. pwm intensity control the MAX7314 includes an internal oscillator, nominally 32khz, to generate pwm timing for led intensity con- trol or other applications such as pwm trim dacs. pwm can be disabled entirely for all the outputs. in this case, all outputs are static and the MAX7314 operating current is lowest because the internal pwm oscillator is turned off. the MAX7314 can be configured to provide any combi- nation of pwm outputs and glitch-free logic outputs. each pwm output has an individual 4-bit intensity con- trol (table 14). when all outputs are to be used with the same pwm setting, the outputs can be controlled together instead using the global intensity control (table 13). table 10 shows how to set up the MAX7314 to suit a particular application. pwm timing the pwm control uses a 240-step pwm period, divided into 15 master intensity timeslots. each master intensity timeslot is divided further into 16 pwm cycles (figure 12). the master intensity operates as a gate, allowing the indi- vidual output settings to be enabled from 1 to 15 timeslots per pwm period (figures 13, 14, 15) (table 13). MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 15 table 5. ports configuration registers register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 ports configuration p7?0 (1 = input, 0 = output) 0 read back ports configuration p7?0 1 0x06 op7 op6 op5 op4 op3 op2 op1 op0 ports configuration p15?8 (1 = input, 0 = output) 0 read back ports configuration p15?8 1 0x07 op15 op14 op13 op12 op11 op10 op9 op8 table 6. input ports registers register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 read input ports p7?0 1 0x00 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 read input ports p15?8 1 0x01 ip15 ip14 ip13 ip12 ip11 ip10 ip9 ip8 table 7. blink logic blink enable flag e blink flip flag b blink input pin blink flip flag exor blink input pin blink function output registers used 0 x x x disabled blink phase 0 registers 0 0 0 blink phase 0 registers 0 1 1 blink phase 1 registers 1 0 1 blink phase 1 registers 1 11 0 enabled blink phase 0 registers
MAX7314 each output? individual 4-bit intensity control only operates during the number of timeslots gated by the master intensity. the individual controls provide 16 intensity settings from 1/16 through 16/16 (table 14). figures 16, 17, and 18 show examples of individual intensity control settings. the highest value an individ- ual or global setting can be set to is 16/16. this setting forces the output to ignore the master control, and fol- low the logic level set by the appropriate blink phase register bit. the output becomes a glitch-free static out- put with no pwm. using pwm intensity controls with blink disabled when blink is disabled (table 7), the blink phase 0 reg- isters specify each output? logic level during the pwm on-time (table 8). the effect of setting an output? blink phase 0 register bit to zero or 1 is shown in table 11. with its output bit set to zero, an led can be controlled with 16 intensity settings from 1/16th duty through fully on, but cannot be turned fully off using the pwm inten- sity control. with its output bit set to 1, an led can be controlled with 16 intensity settings from fully off through 15/16th duty. using pwm intensity controls with blink enabled when blink is enabled (table 7), the blink phase 0 regis- ters and blink phase 1 registers specify each output? logic level during the pwm on-time during the respective blink phases (tables 8 and 9). the effect of setting an output? blink phase x register bit to zero or 1 is shown in table 12. leds can be flipped between either directly on and off, or between a variety of high/low pwm intensities. global/o16 intensity control the 4 bits used for output o16? pwm individual inten- sity setting also double as the global intensity control (table 13). global intensity simplifies the pwm settings when the application requires them all to be the same, such as for backlight applications, by replacing the 17 individual settings with 1 setting. global intensity is enabled with the global intensity flag g in the configura- tion register (table 4). when global pwm control is used, the 4 bits of master intensity and 4 bits of global intensity effectively combine to provide an 8-bit, 240- step intensity control applying to all outputs. it is not possible to apply global pwm control to a sub- set of the ports, and use the others as logic outputs. to mix static logic outputs and pwm outputs, individual pwm control must be selected (table 10). 18-port gpio with led intensity control, interrupt, and hot-insertion protection 16 ______________________________________________________________________________________ table 8. blink phase 0 registers register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 write outputs p7?0 phase 0 0 read back outputs p7?0 phase 0 1 0x02 op7 op6 op5 op4 op3 op2 op1 op0 write outputs p15?8 phase 0 0 read back outputs p15?8 phase 0 1 0x03 op15 op14 op13 op12 op11 op10 op9 op8 table 9. blink phase 1 registers register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 write outputs p7?0 phase 1 0 read back outputs p7?0 phase 1 1 0x0a op7 op6 op5 op4 op3 op2 op1 op0 write outputs p15?8 phase 1 0 read back outputs p15?8 phase 1 1 0x0b op15 op14 op13 op12 op11 op10 op9 op8
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 17 table 10. pwm application scenarios application recommended configuration all outputs static without pwm set the master, o16 intensity register 0x0e to any value 0x00 to 0xof. the global intensity g bit in the configuration register is don't care. the output intensity registers 0x10 through 0x17 are don't care. a mix of static and pwm outputs, with pwm outputs using different pwm settings set the master and global intensity register 0x0e to any value from 0x10 to 0xff. clear global intensity g bit to zero in the configuration register to disable global intensity control. for the static outputs, set the output intensity value to 0xf. for the pwm outputs, set the output intensity value in the 0x0 to 0xe range. a mix of static and pwm outputs, with pwm outputs all using the same pwm setting as above. global intensity control cannot be used with a mix of static and pwm outputs, so write the individual intensity registers with the same pwm value. all outputs pwm using the same pwm setting set the master, o16 intensity register 0x0e to any value from 0x10 to 0xff. set global intensity g bit to 1 in the configuration register to enable global intensity control. the master, o16 intensity register 0x0e is the only intensity register used. the output intensity registers 0x10 through 0x17 are don't care. figure 12. pwm timing one pwm period is 240 cycles of the 32khz pwm oscillator. a pwm period contains 15 master intensity timeslots 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 1 2 each master intensity timeslot contains 16 pwm cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 16 1 2 figure 13. master set to 1/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . figure 15. master set to 15/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . . figure 14. master set to 14/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . .
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection 18 ______________________________________________________________________________________ figure 17. individual (or global) set to 15/16 master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 next master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 16. individual (or global) set to 1/16 master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 next master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 18. individual (or global) set to 16/16 master intensity timeslot control is ignored 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 table 11. pwm intensity settings (blink disabled) pwm duty cycle output blink phase 0 register bit = 0 pwm duty cycle output blink phase 0 register = 1 output (or global) intensity setting low time high time led behavior when output blink phase 0 register bit = 0 (led is on when output is low) low time high time led behavior when output blink phase 0 register bit = 1 (led is on when output is low) 0x0 1/16 15/16 lowest pwm intensity 15/16 1/16 highest pwm intensity 0x1 2/16 14/16 14/16 2/16 0x2 3/16 13/16 13/16 3/16 0x3 4/16 12/16 12/16 4/16 0x4 5/16 11/16 11/16 5/16 0x5 6/16 10/16 10/16 6/16 0x6 7/16 9/16 9/16 7/16 0x7 8/16 8/16 8/16 8/16 0x8 9/16 7/16 7/16 9/16 0x9 10/16 6/16 6/16 10/16 0xa 11/16 5/16 5/16 11/16 0xb 12/16 4/16 4/16 12/16 0xc 13/16 3/16 3/16 13/16 0xd 14/16 2/16 increasing pwm intensity 2/16 14/16 increasing pwm intensity 0xe 15/16 1/16 highest pwm intensity 1/16 15/16 lowest pwm intensity 0xf static low static low full intensity, no pwm (led on continuously) static high impedance static high impedance led off continuously
applications information hot insertion i/o ports p0?15, interrupt output int /o16, rst input, blink input, and serial interface sda, scl, ad0 remain high impedance with up to 6v asserted on them when the MAX7314 is powered down (v+ = 0v). the MAX7314 can therefore be used in hot-swap applications. output level translation the open-drain output architecture allows the ports to level translate the outputs to higher or lower voltages than the MAX7314 supply. an external pullup resistor can be used on any output to convert the high-imped- ance logic-high condition to a positive voltage level. the resistor can be connected to any voltage up to 5.5v. for interfacing cmos inputs, a pullup resistor value of 220k ? is a good starting point. use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. driving led loads when driving leds, a resistor in series with the led must be used to limit the led current to no more than 50ma. choose the resistor value according to the fol- lowing formula: r led = (v supply - v led - v ol ) / i led where: r led is the resistance of the resistor in series with the led ( ? ). v supply is the supply voltage used to drive the led (v). v led is the forward voltage of the led (v). v ol is the output low voltage of the MAX7314 when sinking i led (v). i led is the desired operating current of the led (a). for example, to operate a 2.2v red led at 14ma from a 5v supply, r led = (5 - 2.2 - 0.25) / 0.014 = 182 ? . MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 19 table 12. pwm intensity settings (blink enabled) examples of led blink behavior (led is on when output is low) pwm duty cycle output blink phase x register bit = 0 pwm duty cycle output blink phase x register = 1 output (or global) intensity setting low time high time low time high time blink phase 0 register bit = 0 blink phase 1 register bit = 1 blink phase 0 register bit = 1 blink phase 1 register bit = 0 0x0 1/16 15/16 15/16 1/16 0x1 2/16 14/16 14/16 2/16 0x2 3/16 13/16 13/16 3/16 0x3 4/16 12/16 12/16 4/16 0x4 5/16 11/16 11/16 5/16 0x5 6/16 10/16 10/16 6/16 0x6 7/16 9/16 9/16 7/16 p hase 0: le d on at l ow i ntensi ty p hase 1: le d on at hi g h i ntensi ty p hase 0: le d on at hi g h i ntensi ty p hase 1: le d on at l ow i ntensi ty 0x7 8/16 8/16 8/16 8/16 output is half intensity during both blink phases 0x8 9/16 7/16 7/16 9/16 0x9 10/16 6/16 6/16 10/16 0xa 11/16 5/16 5/16 11/16 0xb 12/16 4/16 4/16 12/16 0xc 13/16 3/16 3/16 13/16 0xd 14/16 2/16 2/16 14/16 0xe 15/16 1/16 1/16 15/16 p hase 0: le d on at hi g h i ntensi ty p hase 1: le d on at l ow i ntensi ty p hase 0: le d on at l ow i ntensi ty p hase 1: le d on at hi g h i ntensi ty 0xf static low static low static high impedance static high impedance phase 0: led on continuously phase 1: led off continuously phase 0: led off continuously phase 1: led on continuously
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection 20 ______________________________________________________________________________________ table 13. master, o16 intensity register register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb master and global intensity r/ w master intensity o16 intensity write master and global intensity 0 read back master and global intensity 1 m3 m2 m1 m0 g3 g2 g1 g0 master intensity duty cycle is 0/15 (off); internal oscillator is disabled; all outputs will be static with no pwm 0000 master intensity duty cycle is 1/15 0001 master intensity duty cycle is 2/15 0010 master intensity duty cycle is 3/15 0011 master intensity duty cycle is 13/15 1101 master intensity duty cycle is 14/15 1110 master intensity duty cycle is 15/15 (full) 1111 o16 intensity duty cycle is 1/16 0 0 0 0 o16 intensity duty cycle is 2/16 0 0 0 1 o16 intensity duty cycle is 3/16 0 0 1 0 o16 intensity duty cycle is 14/16 1 1 0 1 o16 intensity duty cycle is 15/16 1 1 1 0 o16 intensity duty cycle is 16/16 (static output, no pwm) 0x0e 1 1 1 1
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________________________ 21 table 14. output intensity registers register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb outputs p1, p0 intensity r/ w ttintnit ttintnit write output p1, p0 intensity 0 read back output p1, p0 intensity 1 p1i3 p1i2 p1i1 p1i0 p0i3 p0i2 p0i1 p0i0 output p1 intensity duty cycle is 1/16 0000 output p1 intensity duty cycle is 2/16 0001 output p1 intensity duty cycle is 3/16 0010 output p1 intensity duty cycle is 14/16 1101 output p1 intensity duty cycle is 15/16 1110 output p1 intensity duty cycle is 16/16 (static logic level, no pwm) 1111 output p0 intensity duty cycle is 1/16 0 0 0 0 output p0 intensity duty cycle is 2/16 0 0 0 1 output p0 intensity duty cycle is 3/16 0 0 1 0 output p0 intensity duty cycle is 14/16 1 1 0 1 output p0 intensity duty cycle is 15/16 1 1 1 0 output p0 intensity duty cycle is 16/16 (static logic level, no pwm) 0x10 1 1 1 1 msb lsb msb lsb outputs p3, p2 intensity output p3 intensity output p2 intensity write output p3, p2 intensity 0 read back output p3, p2 intensity 1 0x11 p3i3 p3i2 p3i1 p3i0 p2i3 p2i2 p2i1 p2i0 msb lsb msb lsb outputs p5, p4 intensity output p5 intensity output p4 intensity write output p5, p4 intensity 0 read back output p5, p4 intensity 1 0x12 p5i3 p5i2 p5i1 p5i0 p4i3 p4i2 p4i1 p4i0 msb lsb msb lsb outputs p7, p6 intensity output p7 intensity output p6 intensity write output p7, p6 intensity 0 read back output p7, p6 intensity 1 0x13 p7i3 p7i2 p7i1 p7i0 p6i3 p6i2 p6i1 p6i0
MAX7314 driving load currents higher than 50ma the MAX7314 can be used to drive loads drawing more than 50ma, like relays and high-current white leds, by paralleling outputs. use at least one output per 50ma of load current; for example, a 5v 330mw relay draws 66ma and needs two paralleled outputs to drive it. ensure that the paralleled outputs chosen are controlled by the same blink phase register, i.e., select outputs from the p0 through p7 range, or the p8 through p15 range. this way, the paralleled outputs are turned on and off together. do not use output o16 as part of a load-sharing design. o16 cannot be switched at the same time as any of the other outputs because it is con- trolled by a different register. the MAX7314 must be protected from the negative voltage transient generated when switching off induc- tive loads, such as relays, by connecting a reverse- biased diode across the inductive load (figure 19). the peak current through the diode is the inductive load? operating current. power-supply considerations the MAX7314 operates with a power-supply voltage of 2v to 3.6v. bypass the power supply to gnd with at least 0.047? as close to the device as possible. for the qfn version, connect the underside exposed pad to gnd. 18-port gpio with led intensity control, interrupt, and hot-insertion protection 22 ______________________________________________________________________________________ table 14. output intensity registers (continued) register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb outputs p9, p8 intensity r/ w ttintnit ttintnit write output p9, p8 intensity 0 read back output p9, p8 intensity 1 0x14 p9i3 p9i2 p9i1 p9i0 p8i3 p8i2 p8i1 p8i0 msb lsb msb lsb outputs p11, p10 intensity output p11 intensity output p10 intensity write output p11, p10 intensity 0 read back output p11, p10 intensity 1 0x15 p11i3 p11i2 p11i1 p11i0 p10i3 p10i2 p10i1 p10i0 msb lsb msb lsb outputs p13, p12 intensity output p13 intensity output p12 intensity write output p13, p12 intensity 0 read back output p13, p12 intensity 1 0x16 p13i3 p13i2 p13i1 p13i0 p12i3 p12i2 p12i1 p12i0 msb lsb msb lsb outputs p15, p14 intensity output p15 intensity output p14 intensity write output p15, p14 intensity 0 read back output p15, p14 intensity 1 0x17 p15i3 p15i2 p15i1 p15i0 p14i3 p14i2 p14i1 p14i0 output o16 intensity see master, o16 intensity register (table 13).
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 23 figure 19. diode-protected switching inductive load MAX7314 p8 p10 p0 p1 p2 p3 p4 p5 p6 p7 v+ 2v to 3.6v c sda sda ad0 p11 p12 p13 p14 p15 scl scl blink i/o rst i/o p9 gnd 0.047 f int int/o16 bas16 5v 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v+ sda scl blink p0 ad0 rst top view p15 p14 p13 p12 p4 p3 p2 p1 16 15 14 13 9 10 11 12 p11 p10 p9 p8 gnd p7 p6 p5 qsop MAX7314aeg int/o16 chip information transistor count: 25,991 process: bicmos top view thin qfn MAX7314atg 19 20 21 22 12 3456 18 17 16 15 14 13 23 24 12 11 10 9 8 7 scl v+ sda int/o16 ad0 p0 p1 p2 p3 p4 p5 blink p15 p13 p12 p11 rst p10 p8 p9 gnd p6 p7 p14 pin configurations
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection 24 ______________________________________________________________________________________ qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX7314 18-port gpio with led intensity control, interrupt, and hot-insertion protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. 24l qfn thin.eps package outline, 21-0139 2 1 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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